Search - vhdl random

[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[Other resource] fenpin(vhdl)

Description: 使用VHDL编写的分频程序,能进行任意次的偶数分频,程序简单易懂,供初学者参考-prepared by the use of VHDL-frequency procedures can make even the random frequency, the procedures are simple and easy to understand. reference for beginners
Platform: | Size: 154087 | Author: 黄鹏飞 | Hits:

[Other resource] VHDL-six

Description: 用VHDL语言实现六分频，并且已经通过编译和仿真。由此可举一反三，实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
Platform: | Size: 25473 | Author: philohb | Hits:

[Books] Monte Carlo

Description: 蒙特卡罗(Monte Carlo)方法，或称计算机随机模拟方法，是一种基于“随机数”的计算方法，解决很多计算问题。-Monte Carlo (Monte Carlo) methods, or computer random simulation method, is based on random number is calculated to solve many computing problems.
Platform: | Size: 719872 | Author: 陈子卿 | Hits:

[VHDL-FPGA-Verilog] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[VHDL-FPGA-Verilog] VHDL-six

Description: 用VHDL语言实现六分频，并且已经通过编译和仿真。由此可举一反三，实现任意偶数次分频。-VHDL six minutes frequency, and has been through translation, and simulation. From this we can draw a number at random dual frequency.
Platform: | Size: 25600 | Author: philohb | Hits:

[Other] TCNTL

Description: 用ISE开发的VHDL随机地址发生器,采用循环计数生成地址-using VHDL development of the ISE random address generator, cycle counting generated addresses
Platform: | Size: 634880 | Author: 张稀楠 | Hits:

[Other] prbs

Description: 伪随机序列产生器，VHDL程序，不记得在哪个论坛上下的。-Pseudo-random sequence generator, VHDL procedures, do not remember in which forum from top to bottom.
Platform: | Size: 2048 | Author: 韩丹 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机序列发生器的vhdl算法设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）。 -Pseudo-random sequence generator algorithm VHDL design of a pseudo-random sequence generator, using the generation polynomial for the 1+ X ^ 3+ X ^ 7. RESET has a client request and the two control registers client to adjust the initial value (procedures set of four non-zero initial value optional).
Platform: | Size: 1024 | Author: 文成 | Hits:

[VHDL-FPGA-Verilog] Random_Number_generator

Description: 此代码用于产生系统设计仿真阶段需要的仿真数据，运行的结果是一系列随机数。编译后可生成数据产生模块，在其他工程中之间调用之作为数据输入即可，对vhdl涉及仿真有一定的帮助-This code is used for creating a system design simulation stage of simulation data, the results of running a series of random numbers. Compiler can generate data generated modules, in other works as a call between the data input to the VHDL simulation involves a certain degree of help
Platform: | Size: 35840 | Author: 王弋妹 | Hits:

[VHDL-FPGA-Verilog] Pseudo-random-code

Description: 基于FPGA实现的伪随机序列快速同步.rar-FPGA-based pseudo-random sequence to achieve fast synchronization. Rar
Platform: | Size: 185344 | Author: | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机码发生器的VHDL实现随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Platform: | Size: 217088 | Author: 张之晗 | Hits:

[VHDL-FPGA-Verilog] pn127

Description: 这是个128位的串行伪随机码发生器，还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
Platform: | Size: 446464 | Author: lee | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 8*8乘法器设计伪随机序列发生器 PS2键盘设计均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
Platform: | Size: 2048 | Author: qiumh | Hits:

[Mathimatics-Numerical algorithms] random

Description: 伪随机数产生器,可以根据输入的控制字产生需要的伪随机数-Pseudo-random number generator
Platform: | Size: 2048 | Author: chengaj | Hits:

[VHDL-FPGA-Verilog] trunk-hdlc

Description: 高级链路层协议的实现，vhdl，fpga-- 8 bit parallel backend interface - use external RX and TX clocks - Start and end of frame pattern generation - Start and end of frame pattern checking - Idle pattern generation and detection (all ones) - Idle pattern is assumed only after the end of a frame which is signaled by an abort signal - Zero insertion - Abort pattern generation and checking - Address insertion and detection by software - CRC generation and checking (Optional, external, since CRC-16 or CRC-32 can be used) - FIFO buffers and synchronization (External) - Byte aligned data (if data is not aligned to 8-bits extra random bits are inserted) - Q.921, LAPB and LAPD compliant. - For complete specifications refer to spec document
Platform: | Size: 188416 | Author: | Hits:

[Windows Develop] LFSR

Description: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

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[Other resource] 一些VHDL源代码

[Other resource] fenpin(vhdl)

[Other resource] VHDL-six

[Books] Monte Carlo

[VHDL-FPGA-Verilog] 一些VHDL源代码

[VHDL-FPGA-Verilog] VHDL-six

[Other] TCNTL

[Other] prbs

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] Random_Number_generator

[VHDL-FPGA-Verilog] Pseudo-random-code

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] pn127

[VHDL-FPGA-Verilog] VHDL

[Mathimatics-Numerical algorithms] random

[VHDL-FPGA-Verilog] trunk-hdlc

[Windows Develop] LFSR

[VHDL-FPGA-Verilog] vhdl

[VHDL-FPGA-Verilog] VHDL-source-code

[Other] ZufallszahlengeneratorVHDL

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